NOC DV Sr Engineer
Core
Verification Architect/Engineer responsible for verifying next-generation Infrastructure IPs (DDRSS, Memory Controllers) for System-on-chip (SoC) in smartphones and tablets.
Role type
Senior IC Digital Verification Architect
Builds
Infrastructure IPs for SoCs
Domain
Semiconductor / Hardware Verification
Required skills
UVM, System Verilog, ARM bus protocols, SoC system architecture, Debugging, Functional coverage, Formal verification, Regression testing, Python/Perl scripting
Preferred skills
Low power design optimization, Automotive Safety Integrity Levels (ASIL), Post-silicon bring-up, HW-SW debug, Silicon debug tool chains
Technologies
UVM, System Verilog, Certitude, VC Formal, VPlan, Python, Perl, C/C++, SystemC
Responsibilities
Own DV test bench and associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage), Develop test plans and cases to cover design feature sets, Coordinate with Design and SOC teams on failure debugs and coverage closure, Debug regression signatures and identify bug fixes, Develop/Deploy scripts/tools for validation, Debug and root cause post silicon issues, Work with performance modeling team on latency and bandwidth analysis
Seniority
Senior, hands-on IC
