RISCV CPU Design Verification (Multiple Levels) - Pune
Core
Develop and execute verification plans for high performance and low power RISC-V based CPU designs using simulation and formal verification methodologies.
Role type
Senior IC CPU Design Verification Engineer
Builds
RISC-V CPU cores and SoC components
Domain
Semiconductor / Hardware Engineering / CPU Architecture
Required skills
CPU architecture and micro-architecture knowledge, simulation and formal verification, C/C++, Verilog/SystemVerilog, debugging in simulation/emulation/silicon, power management verification (clock gating, power gating, UPF, DVFS)
Preferred skills
Experience with x86/ARM/MIPS/POWER architectures, DFT and structural debug concepts (JTAG, IEEE1500, MBIST), advanced verification techniques
Technologies
Verilog, SystemVerilog, C, C++, Python, FPGA, Emulators
Responsibilities
Develop and execute verification plans for units and features of a CPU design, Use simulation and formal verification methodologies to execute test plans, Work closely with system architects, design team, software teams and Soc team to validate system use cases, Debug and triage failures in simulation, emulation and/or Silicon, Implementation of assembly and C language tests for verifying CPU architecture
Seniority
Senior, hands-on IC
