Formal Verification Senior Engineer - Qualcomm, Cambridge, UK
Core
Develop deep understanding of 3D Graphics hardware pipeline and feature sets to create assertion-based verification testbenches for GPU architecture.
Role type
Senior IC formal verification engineer (GPU/ASIC)
Builds
Formal Property Verification (FPV) test-plans and assertion-based verification testbenches for GPU RTL
Domain
Semiconductor / Hardware Verification / GPU Architecture
Required skills
Formal Property Verification (FPV), SystemVerilog Assertions (SVA), abstraction techniques, coverage closure, bug-hunting, RTL debugging
Preferred skills
DPV, C2RTL SEQ, RTL2RTL SEQ, GPU Architecture knowledge
Technologies
JasperGold, VC Formal, SystemVerilog
Responsibilities
Develop FPV test-plan, develop assertion-based verification testbench, debug RTL artefacts, achieve formal sign-off matrices, collaborate with global GPU RTL design and DV teams
Seniority
Senior, hands-on IC
