Software Engineer — RISC-V Random Test Generator
Core
Develop a Python-based random test generation (RTG) framework and assembler library for RISC-V CPU design verification, producing ELF binaries to exercise the RVA23.1 ISA.
Role type
Senior IC software engineer (CPU verification toolchain)
Builds
RISC-V CPU design-verification toolchain (RTG framework, assembler library, simulator-coupled generator)
Domain
Semiconductor / CPU Design Verification / RISC-V Architecture
Required skills
Python 3, generator-based coroutines, object-oriented design, RISC-V ISA (instruction encoding, CSR semantics, privilege levels, memory model), virtual memory (Sv39/Sv48), PMP, trap/interrupt handling, RTL verification, ISS development
Preferred skills
Random test generation flows, ISS/RTL co-simulation, compiler development, hypervisor architecture, AIA/IMSIC interrupt architecture, constraint-propagation libraries
Technologies
Python, RISC-V, ELF, RTL, ISS
Responsibilities
Implement generation objects for RISC-V extensions and micro-architectural scenarios; Add instruction forms and encodings to the Python assembler; Write and tune knob-driven test profiles to improve RTL coverage; Work within the privileged-software stack (exception handlers, page tables, PMP, IMSIC); Collaborate with ISS and RTL engineers to triage failures and adjust constraint logic
