SOC Design Verification Engineer– Pre-Si/Post-Si Verification
Core
Verify next-generation SoCs for mobile, AI, high-performance computing, and cloud infrastructure products across pre-silicon simulation/emulation and post-silicon bring-up/validation phases.
Role type
Senior IC SoC verification engineer (Pre-Si/Post-Si)
Builds
Production SoCs and subsystems
Domain
Semiconductor / Hardware Design Verification
Required skills
SystemVerilog, UVM, C/C++, assertion-based verification, coverage-driven verification, RTL debugging, silicon bring-up, ATE/vector debug, computer architecture, digital design fundamentals
Preferred skills
Cache coherency protocols (ACE, CHI, CXL), DDR/HBM memory subsystems, PCIe/CXL/Ethernet verification, AI/ML accelerator verification, emulation platforms (Veloce, Palladium, ZeBu), Trace32, Python/Perl scripting, formal verification, power-aware verification
Technologies
SystemVerilog, UVM, C/C++, Trace32, Veloce, Palladium, ZeBu
Responsibilities
Develop and execute verification plans for SoC and IP-level features; Build and maintain verification environments; Create directed, constrained-random, and stress test scenarios; Debug RTL, testbench, emulation, and silicon issues; Drive coverage closure and regression health; Mentor junior engineers and lead feature-level verification planning.
Seniority
Senior, hands-on IC
