DDRSS Validation Engineer (RTL + Silicon Debug)
Core
End-to-end validation of SoC subsystems (DDR, memory controller, cache, interconnect) across RTL simulation, emulation, and post-silicon environments, with a focus on deep debug and silicon bring-up.
Role type
Senior IC validation engineer (SoC, DDRSS)
Builds
Next-generation SoC platforms
Domain
Semiconductor / SoC Design / Memory Systems
Required skills
SoC validation, RTL/SystemVerilog debugging, firmware development in C, silicon bring-up, memory systems (DDR, cache, interconnect), computer architecture, emulation platforms
Preferred skills
Debugging firmware-driven flows, tool development for validation efficiency, cross-functional collaboration with design and DV teams
Technologies
Verilog, SystemVerilog, C, Emulation platforms, RTL simulation environments
Responsibilities
Drive end-to-end validation of SoC subsystems across simulation, emulation, and silicon; Perform deep debug of functional issues including root-causing failures in RTL simulations and analyzing silicon failures; Develop and maintain production quality firmware in C to manage DDRSS IP sequences and enable bring-up; Validate firmware across simulation, emulation, and silicon platforms; Collaborate cross-functionally with design, DV, and system validation teams; Develop tools, debug infrastructure, and automation to improve validation efficiency.
Seniority
Senior, hands-on IC
