CPU Architecture Performance Engineer (RISC V)
Core
Architect and design state-of-the-art CPUs focusing on performance, energy efficiency, and scalability; model advanced CPU performance features and explore design alternatives.
Role type
Senior IC CPU Architecture Performance Engineer (RISC-V)
Builds
High performance, low power CPUs for next-generation compute products
Domain
Semiconductor / CPU Architecture / RISC-V
Required skills
CPU architecture (fetch, decode, branch prediction, renaming, execute units, SIMD, load/store, MMU, caches, retire), performance modeling, RTL design collaboration, workload analysis, C/C++, scripting (Perl/Python)
Preferred skills
OS internals, compiler technology, performance benchmarks, problem-solving
Technologies
C, C++, Perl, Python, RTL, Performance Simulation Tools
Responsibilities
Identify opportunities for product improvement by collaborating with CPU Performance Architecture and RTL teams; Analyze workloads to identify performance bottlenecks; Perform self-guided performance simulation studies of design alternatives; Write and maintain features and sections of the CPU architectural performance model; Work with RTL and design team to assess implementation cost for new features; Collaborate with performance team to maintain and improve the simulation environment.
Seniority
Senior, hands-on IC
