Senior Design Verification Engineer- Haifa, Hod Hasharon, Ramat Gan
Core
Develop and verify wired and wireless peripheral subsystems integrated into complex SoCs for Snapdragon platforms.
Role type
Senior IC design verification engineer (peripheral IP)
Builds
Peripheral IP and subsystems for Snapdragon SoCs
Domain
Semiconductors / SoC Design
Required skills
UVM, SystemVerilog, constrained-random testing, coverage-driven verification, digital design fundamentals, SoC/IP-level architectures, large-scale regression debugging, scripting (Python/Perl/Tcl/shell)
Preferred skills
High-speed peripheral IPs (USB, PCIe, Display, SerDes), low-power design, reset sequencing, clock-domain interactions, regression management, cross-site team collaboration
Technologies
UVM, SystemVerilog, Python, Perl, Tcl, Linux/UNIX
Responsibilities
Develop and maintain UVM/SystemVerilog verification environments; Own end-to-end verification including testbench architecture, test planning, execution, and coverage closure; Verify IP and subsystem level peripherals integrated into complex SoCs; Debug complex issues in large-scale regression environments
Seniority
Senior, hands-on IC
