DRAM Circuit Designer, up to Staff
Core
Design and optimize custom DRAM circuits and architectures for memory-centric compute systems to improve bandwidth, latency, power, thermal, and area efficiency.
Role type
Senior IC DRAM circuit designer
Builds
Custom DRAM memory cores and architectures for data center, mobile, compute, and XR systems
Domain
Semiconductor / Memory / High-speed digital design
Required skills
Mixed-signal design, layout, and simulation, High-speed design principles, Memory array and datapath design, Verilog/Verilog-A/Verilog-AMS modeling, EDA tools, Matlab, Python, Memory architecture, Buses, 2.5D/3D integration
Preferred skills
DRAM architecture performance assessment, C/C++/Python programming, DRAM datasheets and IO interfaces knowledge
Technologies
EDA tools, Matlab, Python, Verilog, Verilog-A, Verilog-AMS
Responsibilities
Design and optimize memory core circuits for higher sense margin and improved array timing, Develop and optimize DRAM circuits and timing control for performant, area, and energy efficient cell array, Develop bank array placement strategies across various bank array, TSV, and power distribution choices, Develop novel fabrics for best/robust distribution of high-bandwidth busses across the DRAM array, compute, and IO, Create layouts that optimize circuit placement, signal routing, and power delivery, Develop robust power delivery to the array design, Use state-of-the-art design and simulation tools to simulate the circuit behavior and manufacturability readiness, Develop behavioral, timing, and power models of the circuits to guide the architecture choices across AI, compute, and mobile workloads, Floorplan DRAM circuits under manufacturing constraints, testability, repairability, and high performance
Seniority
Senior, hands-on IC
