Power Integrity Design Engineer – PDN / EMIR - Cork, Ireland
Core
Perform power integrity analyses (IR-drop, Electromigration) for high-performance, low-power ASICs and SOCs to ensure power grid quality and Vmin compliance.
Role type
Senior IC Power Integrity Design Engineer (PDN/EMIR)
Builds
High-performance, low-power ASIC solutions and Snapdragon Cores/SOCs
Domain
Semiconductor / ASIC Design / Power Integrity
Required skills
Power integrity analysis (IR-drop, EM), ASIC design flows (RTL-to-GDS), Power grid quality assessment, Vmin optimization, Automation (Python/TCL/Perl), PDN/EMIR tools (RedHawk, RHSC, Voltus, PTPX)
Preferred skills
Package design, System-level PDN analysis, Thermal analysis, Multi-die ICs (2.5D/3D)
Technologies
RedHawk, RHSC, Voltus, PTPX, Python, TCL, Perl
Responsibilities
Perform PDN checks (IR-drop, ESD, EM) for complex cores and full-chip SOCs, Develop new techniques for PDN analysis and sign-off, Collaborate with Physical Design and STA teams for Vmin assessment, Automate power and PDN data mining and processing, Ensure compliance with power integrity signoff checklists, Anticipate and resolve PDN issues across development phases
Seniority
Senior, hands-on IC