CPU Verification Engineer (RISC-V)
Core
Design Verification Engineer validating CPU and SOC level micro-architectures to ensure launch readiness.
Role type
Senior IC CPU Verification Engineer (RISC-V)
Builds
CPU and System-on-Chip (SoC) designs
Domain
Semiconductor / CPU Architecture
Required skills
RISC-V instruction set architecture, Micro-processor verification, Cache coherence, Memory ordering and consistency, Prefetching, Branch prediction, Renaming, Speculative execution, Address translation, Random Instruction Sequencing (RIS), Formal verification, Assertions, Silicon bringup, Testbench development, Assembly code, Verification methodologies, Gate-level simulation, Coverage collection
Preferred skills
Leading small verification teams, Mixed signal verification, Debugging test failures
Technologies
Simulators, Coverage collection tools, Gate-level simulation tools, Waveform viewers
Responsibilities
Develop detailed Test and Coverage plans, Develop Verification environment (Stimulus, Checkers, Assertions, Trackers), Execute Verification Plans including Design Bring-up and Regressions, Debug test failures, Track and report DV progress using metrics
Seniority
Senior, hands-on IC
