GPU Validation and Emulation Engineer, Senior
Core
Architect, design, implement, verify, and optimize the performance and power of GPU cores, focusing on hardware emulation and system-level debugging.
Role type
Senior IC GPU Validation and Emulation Engineer
Builds
High-performance GPU cores and emulation environments for next-generation mobile and connected devices
Domain
Semiconductor / GPU Architecture / Hardware Emulation
Required skills
Verilog RTL synthesis, FPGA implementation, hardware emulation platforms (Veloce/Palladium/Zebu), system-level debugging, C/C++ programming, Python/Tcl/Perl scripting, UVM/System Verilog, RTL simulation
Preferred skills
GPU/CPU/DDR/Bus architecture knowledge, post-silicon debug experience, hybrid emulation methodologies, waveform analysis
Technologies
Veloce, Palladium, Zebu, Xilinx FPGAs, Altera FPGAs, UVM, System Verilog, C, C++, Python, Tcl, Perl
Responsibilities
Synthesize Verilog RTL and create models for emulation platforms; Develop hardware emulator implementation including design partitioning, synthesis, place and route, and timing analysis; Drive debug failures on emulators and collaborate with designers and SW driver teams; Work with tool vendors to improve synthesized FPGA RTL area/performance; Integrate third-party IP and perform system-level debugging; Support chip bring up and post silicon debug; Debug functional and timing models
Seniority
Senior, hands-on IC
