CPUSS Verification (Power Management), Staff/ Senior Staff
Core
Drive end-to-end verification of next-generation CPU Co-Processor (CPUCP/PDP) Power Management firmware and hardware features.
Role type
Staff/ Senior Staff IC hardware verification engineer (power management)
Builds
Next-generation CPU platforms (SoC)
Domain
Semiconductor / Hardware Engineering
Required skills
SystemVerilog, UVM, C/C++, Python, AMBA protocols, NoC verification, RTL simulation, emulation, waveform analysis, coverage closure, power management validation (DVFS, LPM), automation frameworks
Preferred skills
Pre-silicon verification methodologies, CI/CD verification workflows, mentoring engineers, cross-team technical leadership
Technologies
SystemVerilog, UVM, C/C++, Python, AMBA, NoC
Responsibilities
Architect and develop robust SystemVerilog/UVM testbenches, transactors, checkers, and verification infrastructure for complex SoC subsystems; Define and implement comprehensive validation for power-management features such as DVFS, Low Power Modes (LPM), clock/power transitions, and firmware-controlled sequences; Lead complex debug and root-cause analysis across Firmware, RTL, Design, Emulation, and Post-Silicon teams; Own verification planning, test strategy, coverage modeling, coverage closure, and functional signoff; Mentor junior engineers and foster a culture of technical excellence, ownership, and innovation; Drive cross-functional initiatives spanning Firmware, Hardware Design, Emulation, and Post-Silicon Verification teams.
