MTS Yield Deviation/YT Engineer
Core
Lead efforts to identify, characterize, and resolve yield loss mechanisms impacting manufacturing performance in high-volume semiconductor operations.
Role type
Senior IC yield deviation and tail analysis engineer
Builds
Production memory and storage products
Domain
Semiconductor manufacturing (memory/storage)
Deliverable
production ML models
Required skills
Semiconductor physics, transistor operation, scaling limitations, reliability fundamentals, CMOS characterization, statistical analysis, root cause investigation, defect characterization, failure analysis, data analysis (JMP, Python), hypothesis-driven problem solving
Preferred skills
DRAM manufacturing, yield-tail analysis, RDA, AI-assisted analytics, automation development
Technologies
JMP, Python, AI-enabled tools, EFA, PFA
Responsibilities
Monitor probe yield performance to identify deviations and failure signatures; Lead MBPS and root cause investigations using statistical analysis and fault trees; Drive defect characterization and failure analysis activities; Partner with cross-functional teams to implement corrective actions; Develop and deploy analytics, dashboards, and AI-enabled workflows.
Seniority
Senior, hands-on IC