Silicon Validation Engineer, Senior
Core
Characterize analog blocks, bring up silicon, debug issues, and perform PHY/Link Layer/Protocol compliance testing for high-performance, low-power world-class products.
Role type
Senior Silicon Validation Engineer (ASIC/SerDes)
Builds
High-performance, high-quality, low-power ASICs and SoCs for communication and data processing
Domain
Semiconductors / Hardware Validation / SerDes / PCIe / Ethernet
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog block characterization, SerDes architecture (NRZ, PAM4), PHY/Link Layer/Protocol compliance testing, Silicon bring-up and debugging, Test plan and regression test methodology development, Test script automation (Python, Perl, C/C++), Test equipment automation (Scope, BERT, Logic Analyzer, VNA), Signal integrity and power integrity analysis, PCB design knowledge, Compliance software usage (SIGTEST, SEASIM, COM)
Preferred skills
PCIe and Ethernet protocol layer experience, MAC and PCS design block knowledge, Optical and die2die validation experience, Data post-processing and analysis (Mango Database, HTML, JavaScript, Numpy, SciPy, Seaborn, Matplotlib)
Technologies
PCIe (Gen1 to Gen6), IEEE 100G CK, OIF 100G CEI, 224G, UCIe, Python, Perl, Matlab, C/C++, HTML5, SIGTEST, SEASIM, COM, Mango Database, Numpy, SciPy, Seaborn, Matplotlib
Responsibilities
Characterize analog blocks and perform PHY/Link Layer/Protocol compliance against industry standards; Bring up silicon, debug issues, present test results, and generate validation reports; Define validation and regression test plans and develop test methodologies; Develop and standardize test scripts for validation and regression tests covering compliance and design features; Determine equipment and accessories needs for various tests and automate test equipment; Study signal integrity and power integrity for evaluation boards and for silicon
Seniority
Senior, hands-on IC