Senior Memory Design Engineer
Core
Design, layout, and optimization of DRAM Memory array/Peripheral Logic/Analog circuits using AI-based tools and automation frameworks.
Role type
Senior IC memory design engineer (DRAM)
Builds
High-performance DRAM memory products
Domain
Semiconductor / Memory / Analog Circuit Design
Deliverable
production ML models
Required skills
CMOS circuit design, device physics, memory operation, SPICE-based simulation, parasitic extraction, floor-planning, placement, routing, circuit-level verification
Preferred skills
DRAM design (DDR5, LPDDR5, HBM), NAND memory design, SoC/ASIC semicustom flow, AI/ML-assisted design flows
Technologies
SPICE, EDA tools, Micron-specific simulators
Responsibilities
Assist with overall design, layout, and optimization of DRAM Memory array/Peripheral Logic/Analog circuits; Leverage AI-based tools for schematic optimization and design-space exploration; Perform parasitic analysis, sensitivity studies, and corner coverage; Improve debug efficiency across simulation and silicon learning loops; Define semicustom methodology for memory design; Collaborate with CAD, EDA, and software teams to integrate AI-driven flows; Oversee and manage the layout process including floor-planning, placement, and routing; Perform circuit-level verification including functional, timing, power and reliability analysis
Seniority
Senior, hands-on IC
