Senior Staff System & Modeling Engineer – Wireline Communications
Core
Architect, model, and verify high-speed wireline communication systems and analog/mixed-signal blocks to enable accurate simulations and validate architectural decisions for next-generation interconnect technologies.
Role type
Senior Staff System & Modeling Engineer (Wireline Communications)
Builds
High-speed wireline and optical products, analog IPs, and system-level verification models.
Domain
Semiconductor, Data Infrastructure, Wireline Communications, Analog/Mixed-Signal
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System-level architecture, Digital Signal Processing (DSP), Analog/Mixed-Signal circuit behavior, Equalization techniques (CTLE, FFE, DFE), SerDes standards (PCIe, UCIe), Behavioral modeling, HDL (SystemVerilog/Verilog), MATLAB/Simulink, C/C++, Python
Preferred skills
Mentorship, Technical documentation, Lab testing and debugging, Cross-functional collaboration
Technologies
MATLAB, Simulink, SystemVerilog, C, C++, Python, PCIe, UCIe
Responsibilities
Architect and model end-to-end wireline communication systems; Devise novel DSP techniques for ultra-high-speed systems; Develop models capturing performance and impairments of analog blocks; Collaborate with system architects to explore design trade-offs; Model analog/mixed-signal circuit blocks for functional verification; Support lab testing, debugging, and silicon bring-up; Mentor junior engineers and author technical documentation.
Seniority
Senior Staff, hands-on IC with technical leadership