SMTS, Design Rule Enablement Team TPG
Core
Lead Design Enablement efforts for DRAM technologies by coordinating cross-functional engineering teams to develop and optimize design rules, requirements, and test structures from early development through manufacturing.
Role type
Senior Member of Technical Staff (IC)
Builds
DRAM products and advanced CMOS technologies
Domain
Semiconductor manufacturing / Memory and storage
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DRAM process flow expertise, PDK development, Test Structure Design and Characterization, Design Rule Checks (DRC), Layout task execution, Process Integration knowledge, Advanced Mask Design collaboration, Database layout techniques, AI framework utilization, LLM workflow development
Preferred skills
Experience with GAA, FinFET, Sense Amp, Word-line driver, Anti-Fuse technologies
Technologies
Cadence, Siemens, AI frameworks, LLMs
Responsibilities
Develop and refine Design Rules, Requirements, and Test Structures for all DRAM generations; Define milestones for projects within the layout schedule; Manage test structure evaluation to support next-gen device development; Address process window vs. die size issues arising from database layout techniques; Ensure robust Design Rule Checks (DRC) and appropriate responses to deviations; Document and communicate complex problem resolutions and drive cross-node design rule alignment; Improve documentation of R&D activities for design rule improvement; Define and implement design rules within APR workflows to enhance layout efficiency and manufacturability; Utilize AI framework and develop workflow compatible with LLMs & other GenAI techniques for efficiency gain
Seniority
Senior, hands-on IC