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Principal Engineer/MTS, DRAM PI

Hiroshima, Japan💼 Full-time🗓 2026-07-14 → 2026-09-25

Core

Leading process integration activities for next-generation DRAM technology development, focusing on capacitor module design and cross-module integration.

Role type

Principal Engineer, Semiconductor Process Integration

Builds

Next-generation DRAM nodes and high-performance memory/storage products

Domain

Semiconductor manufacturing / Memory technology

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

Semiconductor process knowledge, Process integration expertise, DOE design and execution, Data analysis, Yield and quality optimization, Cross-functional collaboration

Preferred skills

DRAM device and structure knowledge

Technologies

Semiconductor fabrication tools, DOE methodologies

Responsibilities

Develop and integrate process technologies for future DRAM nodes, Design and optimize capacitor modules, Execute experiments and analyze data to optimize process conditions, Identify and resolve yield and quality issues, Collaborate with process, design, device, and quality teams

Seniority

Principal, hands-on IC with strategic oversight

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