Principal HBM Design Architect
Core
Design, simulate, analyze, and floorplan digital and analog DRAM circuits for next-generation high-bandwidth memory (HBM) solutions using 3D stacking and TSV-based integration.
Role type
Senior IC analog/digital circuit design engineer (HBM)
Builds
High-performance, low-power HBM memory products
Domain
Semiconductor / Memory / High-speed interface
Deliverable
production ML models | product features
Required skills
CMOS circuit design, device physics, schematic entry, HSPICE/FineSim simulation, power distribution analysis, scripting (Python/Tcl/Perl)
Preferred skills
DRAM subsystem design, high-speed interface circuits, analytical problem-solving
Technologies
HSPICE, FineSim, Python, Tcl, Perl, 3D stacking, TSV
Responsibilities
Design and optimize data path, ECC, command/control, and high-speed timing structures; Evaluate full-chip and block-level functionality; Perform timing, area, power, and complexity analysis; Conduct pathfinding studies for future architectures; Collaborate with build, verification, and packaging teams; Analyze circuit behavior under PVT and parasitic conditions
Seniority
Senior, hands-on IC