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Distinguished Engineer Digital Asic

Butterfly offers a hybrid work model for most positions, with team members spend💼 Full-time💰 $230,000–$230,000🗓 2026-07-27

Core

Architecting and owning complex digital IC subsystems for Ultrasound-on-Chip™ semiconductor technology, from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff.

Role type

Distinguished Engineer Digital ASIC

Builds

Proprietary Ultrasound-on-Chip™ semiconductor chips and software solutions for portable medical imaging devices.

Domain

Medical imaging / Semiconductor hardware design

Deliverable

production ML models | product features | infrastructure

Required skills

Digital IC/ASIC/SoC design, RTL ownership, SystemVerilog/Verilog, timing closure, clock/reset domain architecture, power-aware design, PPA tradeoffs, high-throughput datapath architecture, SRAM/memory hierarchy design, advanced technology node integration (28nm or smaller), cross-functional hardware-firmware interface design

Preferred skills

Compute-intensive digital pipelines (DSP, beamforming, AI, MAC-heavy), medical imaging/ultrasound systems knowledge, programmable digital compute blocks (AI accelerators, MPUs, eFPGA fabrics)

Technologies

SystemVerilog, Verilog, 28nm and smaller nodes

Responsibilities

Own complex digital IC subsystems from architecture through tapeout, implement silicon-proven digital architectures, architect high-throughput digital datapaths, collaborate with verification teams for signoff, work cross-functionally with analog/systems/packaging teams

Seniority

Distinguished Engineer, hands-on IC architecture & implementation

Rewrite
## About the Company Butterfly Network, Inc. (NYSE: BFLY) is driving a digital revolution in ultrasound imaging and sensing with its proprietary Ultrasound-on-Chip™ semiconductor technology and software solutions. Butterfly first proved its technology in the point-of-care ultrasound market – commercializing the world's first single-probe, whole-body portable ultrasound device, which is now on its best-selling, third-generation: Butterfly iQ3™. The Company combines its advanced hardware with cloud software and AI, an enterprise workflow solution (Compass AI™) and other offerings to drive adoption of affordable, accessible ultrasound. Butterfly also enables third-party development of imaging AI apps through Butterfly Garden™, its software development kit and AI partnership initiative. In addition to its medical imaging products, Butterfly Embedded™ is the Company's Ultrasound-on-Chip™ licensing and co-development program designed to enable a new wave of ultrasound-enabled technologies across non-competitive healthcare markets and beyond. Through Butterfly Embedded™, partners can build and scale novel ultrasound applications powered by Butterfly's proprietary semiconductor chip and software platform. Butterfly's innovations have been recognized by Prix Galien USA, Fierce 50, TIME's Best Inventions and Fast Company's World Changing Ideas, among other achievements. We're a team of bold thinkers, problem-solvers, and innovators ready to shape the future of medical imaging. Let's build something extraordinary together! ## About the Role We are looking for a Principal level digital IC / ASIC / SoC designer to join our team. This role involves owning complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design. ## Responsibilities - Own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design. - Collaborate with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff. - Work cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts). ## Qualifications ### Baseline skills/experiences/attributes - BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience. - 8–12+ years (typical Principal level) in digital IC / ASIC / SoC design with significant hands-on RTL ownership. - Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power-aware design, and PPA (power, performance, area) tradeoffs. - Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces. - Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design. - Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third-party IP. ### Ideally, you also have these skills/experiences/attributes - Experience implementing compute-intensive digital pipelines (e.g., DSP, beamforming, AI, or MAC-heavy/vector datapaths). - Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures. - Experience designing or integrating programmable digital compute blocks (e.g., AI accelerators, MPUs, or eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs. ## Values Innovation is what we do. Our values are how we make it happen. Butterflies are and believe in… - Patient-Centric Innovators: Our mission is THE mission. - Empowered to Impact: Every voice matters. - One Team, One Goal: Unity fuels progress. - Growth Champions: We embrace challenges. - Action-Oriented Achievers: We follow through, every time. ## Location Butterfly offers a hybrid work model for most positions, with team members spending two or more days a week in the office. While flexibility is key, we value in-person connections that spark creativity and teamwork. Our offices are designed for collaboration, with comfortable workspaces, stocked kitchens, and opportunities to connect with peers. For this role, location will depend on candidate qualifications and experience. This role may be based out of one of our U.S. offices, including: - SF Bay Area - Burlington, MA ## Benefits and Perks - Comprehensive health insurance, encompassing dental and vision coverage, is provided to all our employees. As a health-tech company, we prioritize the well-being of our teams. We also contribute to Health Savings Account (HSA) accounts for all enrolled employees on an annual basis. - Comprehensive Employee Assistance Program - we provide access to tools and resources to support your emotional health and day-to-day needs. - 401k plan and match - we facilitate your retirement goals. - Eligible employees will have the opportunity to participate in Employee Stock Purchase Plan (ESPP). - Unlimited Paid Time Off + 10 Holiday Days a Year - recharge and come back ready to make an impact. - Parental Leave - we aim to provide our employees with time to bond with their growing family, along with additional support for primary caregivers to help transition back to work. - Competitive salaried compensation - we value our employees and show it. - Equity - we want every employee to be a stakeholder. - The opportunity to build a revolutionary healthcare product and save millions of lives! ## Compensation This role in the SF Bay Area offers a competitive base salary around $260,000, along with bonus, equity, and comprehensive benefits. Compensation is determined based on skills, qualifications, experience, and market demand. This role in Burlington, MA offers a competitive base salary around $230,000, along with bonus, equity, and comprehensive benefits. Compensation is determined based on skills, qualifications, experience, and market demand.
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