Design Verification Intern, BS - Summer 2027
Core
Develop automated tests and simulation environments to verify the architecture of cutting-edge processors and SoC designs, focusing on finding and troubleshooting hidden flaws in chips.
Role type
Design Verification Intern (BS)
Builds
Simulation environments and automated testbenches for pre-silicon emulation and verification of ODSP-related chips, ASIC designs, and network connectivity solutions.
Domain
Semiconductor / Hardware Design / Data Infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog, VLSI, VHDL, UVM, Python, C, C++, Perl, Java, RTL integration, hardware/software interaction debugging, test coverage analysis
Preferred skills
Experience with Synopsys, Cadence, or Mentor tools, knowledge of computer architecture, logic, processor, memory system, analog, and integrated circuit design
Technologies
Synopsys, Cadence, Mentor, UVM, Verilog, VHDL
Responsibilities
Create powerful simulation environments that mimic real-world conditions, develop smart automated tests to push designs to their limits, analyze test coverage results & metrics, collaborate with chip architects and designers to solve complex problems
Seniority
Intern
