Design Verification Intern, BS - Summer 2027
Core
Intern role creating simulation environments and automated tests to verify next-generation cloud, AI, storage, and networking chip designs.
Role type
Design Verification Intern
Builds
Simulation environments and automated testbenches for ASIC/SOC designs
Domain
Semiconductor / Hardware Verification
Required skills
Verilog, VLSI, VHDL, UVM, Python, C, C++, Perl, Java, RTL integration, hardware/software debugging
Preferred skills
Computer architecture, logic design, processor design, memory system design, analog design, SoC/ASIC design, signals and signal processing
Technologies
Synopsys, Cadence, Mentor
Responsibilities
Create powerful simulation environments mimicking real-world conditions, develop smart automated tests to break designs and find flaws, analyze test coverage results and metrics, collaborate with chip architects and designers to solve complex problems
Seniority
Intern
