Design Verification Intern
Hybrid · United States
Core
Verify circuitry inside Marvell's OCTEON SoC chips for data infrastructure, ensuring designs meet customer specifications for telecom and automotive markets.
Role type
Design Verification Engineer (Intern)
Builds
SoC families of multi-core CPU processors and Radio Access SoCs for 5G platforms
Domain
Semiconductor / VLSI / Networking
Required skills
Verilog, System Verilog, VLSI design, simulation tools (Synopsys VCS, Cadence, Mentor), Python scripting, Linux environment, testbench creation, circuit analysis
Preferred skills
Experience with DFT engineers, presenting test plans to review committees
Technologies
Verilog, System Verilog, Synopsys VCS, Python, Linux
Responsibilities
Debug RTL designs using System Verilog, run simulations, collaborate with RTL and DFT engineers, present test plans for larger blocks
Seniority
Intern
