Senior Staff Design Engineer - PCIE/CXL Subsystem COE
Core
Design, verify, and deliver IP subsystem building blocks for PCIe/CXL, Ethernet, and memory technologies powering custom chips for hyperscale cloud, AI, and data center customers.
Role type
Senior Staff Design Engineer (RTL/Architecture)
Builds
Production-ready IP subsystems for PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, and Low-Speed IO
Domain
Semiconductor / Data Infrastructure / Custom Cloud Solutions
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design (System Verilog/Verilog), PCIe/CXL specifications, ARM-based SoC integration, AMBA protocols (AXI-4, CHI, ACE), Clocking/Resets/CDC/RDC, low-power techniques, EDA tools (Synopsys/Cadence), scripting (TCL/Perl/Python), version control (GIT/SVN)
Preferred skills
End-to-end subsystem RTL design execution, high-performance low-latency data path design, post-silicon bring-up and debug, technical leadership and mentoring
Technologies
System Verilog, Verilog, PCIe, CXL, AXI-4, CHI, ACE, Synopsys, Cadence, TCL, Perl, Python, GIT, SVN
Responsibilities
Define micro-architecture and implement RTL for PCIe/CXL subsystems; collaborate with Architecture to translate requirements into robust designs; work with Verification on test plans, debug, and coverage closure; partner with Physical Design and DFT teams; support silicon bring-up and post-silicon debug; drive design quality improvements and reuse; participate in design reviews; mentor junior designers
Seniority
Senior Staff, hands-on IC with technical leadership
