RTL Design Principal Engineer
Core
Define subsystem architecture, micro-architecture, and register specifications for highly complex SoCs and implement them using RTL coding techniques.
Role type
Principal RTL Design Engineer (SoC/ASIC)
Builds
Custom ASIC business, Cloud AI solutions, Enterprise/Carrier solutions including CXL product line
Domain
Semiconductor, Data Infrastructure, SoC Design
Deliverable
production ML models | product features
Required skills
Verilog/System Verilog RTL coding, System Verilog assertions, Full Chip Integration, Complex SoC design, Subsystem and block level architecture, Specification writing, Cross-functional collaboration
Preferred skills
Networking, Embedded systems architecture, Computer architecture, Machine learning accelerators, Scripting in Perl/Python/Shell
Technologies
Verilog, System Verilog, Perl, Python, Shell
Responsibilities
Define sub system architecture, micro-architecture and register specification; Conduct detailed performance, architectural and design requirement reviews; Implement a specification using RTL coding techniques; Work with physical design teams on floorplanning, power analysis, synthesis and timing signoff; Work with verification team on pre-silicon verification tasks; Provide mentorship to junior team members
Seniority
Principal, hands-on IC with mentorship
