Distinguished Engineer, Switch Architect
Core
Define architecture for Marvell's next-generation AI networking switch ASICs designed for hyperscale cloud and ML/AI-driven workloads.
Role type
Distinguished Engineer, Switch Architect
Builds
Next-generation AI networking switch ASICs for hyperscale cloud and ML/AI workloads
Domain
Semiconductor / Data Center Networking / AI Infrastructure
Deliverable
production ML models | product features
Required skills
Large-scale ASIC architecture, High-speed interconnects and Ethernet protocols, Traffic management architectures, Packet processing, Scaling networks in AI training and inference fabrics, Performance modeling and simulation, Architectural trade-off analysis, C/C++, Python
Preferred skills
Standards development (Ultra Ethernet, UAL), Mentorship of engineering teams, Cross-functional leadership
Technologies
C, C++, Python, Modeling environments
Responsibilities
Define architecture for next-generation AI networking switch ASICs, Anticipate and analyze emerging technology trends to influence long-term roadmap, Contribute to development of industry standards including Ultra Ethernet and UAL, Create and maintain architectural and performance models, Collaborate with silicon, software, systems, and product teams, Document architecture concepts and specifications, Represent Marvell in standards bodies and strategic customer discussions, Provide architectural mentorship and leadership
Seniority
Distinguished, Strategy & Mentorship
