Staff Digital Design Engineer
Core
Lead digital design architecture, RTL implementation, and low-power design for power management chips (PMIC, controllers, drivers) serving consumer, industrial, and automotive markets.
Role type
Staff Digital Design Engineer (Power Management ICs)
Builds
Power management products including DC-DC PMIC/POL, multiphase controllers, LED drivers, and SiC drivers
Domain
Semiconductor / Power Electronics / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital RTL design, ASIC synthesis, timing analysis, CDC, System Verilog, Verilog, TCL, Perl, Python, XML, Power converter topologies, Digital architecture trade-offs
Preferred skills
Experience with SOCV, Emulation, FPGA, Post-silicon validation, MCU systems
Technologies
Verilog, TCL, Perl, Python, XML, UPF, System Verilog
Responsibilities
Lead digital design architecture and RTL teams; Drive architecture to micro-architecture to RTL implementation; Support bring-up on pre-silicon platforms (SOCV, Emulation, FPGA); Own technical outcome of design and verification; Identify and implement new tools and processes; Support post-silicon validation
Seniority
Staff, hands-on IC leadership