Design Verification Engineer
Core
Confirming functionality and performance of analog and mixed signal integrated circuits during the IC design phase by developing simulation test benches and automated checkers.
Role type
Design Verification Engineer (Analog/Mixed-Signal)
Builds
Simulation test benches, automated checkers, Spec Compliance Matrix, regression scripts
Domain
Semiconductor / Analog and Mixed-Signal IC Design
Required skills
SPICE simulation, SystemVerilog, Verilog, VHDL, analog circuit fundamentals, regression analysis, coverage tracking
Preferred skills
C/C++/Python, power management (switching regulators, LDOs), ADC/DAC design, behavioral modeling (Verilog-A, Verilog-AMS), digital circuit design
Technologies
Cadence Virtuoso, SystemVerilog, SPICE, Verilog, VHDL, Python, C/C++
Responsibilities
Develop detailed verification plans, implement mixed-signal testbenches, run coverage regressions, track verification status and issues, contribute to DV strategy improvements
Seniority
Entry-level (Bachelors required, Masters preferred, Career Accelerator Program)
