ASIC Engineering Technical Leader
Core
Architect, develop, and deploy Automated Test Equipment (ATE) solutions for complex ASICs and SoCs, owning the lifecycle from pre-silicon DFT to high-volume manufacturing.
Role type
Senior IC ASIC Test Development Technical Leader
Builds
Automated Test Equipment (ATE) solutions and test programs for wafer sort and final test
Domain
Semiconductor manufacturing / ASIC testing
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ATE test program development, C/C++/Python/Perl scripting, DC/AC parametric testing, digital vector execution, mixed-signal testing, high-speed SerDes testing, advanced packaging (2.5D/3D, chiplets), DFT architectures (ATPG, Logic BIST, Memory BIST, JTAG), complex silicon debugging
Technologies
Advantest V93000 (SmarTest), oscilloscopes, BERTs, logic analyzers
Responsibilities
Architect and debug complex ATE test programs for wafer sort and final test; Lead first-silicon ATE bring-up and validation of networking processors and multi-die packages; Partner with DFT teams to define testability requirements and simulate test vectors; Drive Test Time Reduction (TTR) and yield optimization initiatives; Lead transfer of test programs to OSAT partners and resolve manufacturing issues; Mentor junior engineers and drive continuous improvement in test methodologies
Seniority
Senior, hands-on IC
