Emulation Engineer, Technical Leader
Core
Design, develop, and test complex emulation environments and infrastructure to evaluate the performance and functionality of multi-terabit networking systems before silicon production.
Role type
Senior Emulation Engineer (Technical Lead)
Builds
Pre-silicon emulation infrastructure and test environments for Cisco's core switching and routing ASICs.
Domain
Networking hardware / ASIC design / Pre-silicon validation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Emulation platform expertise (Palladium, Veloce, Zebu), C/C++ and TCL infrastructure development, RTL development for emulation prototypes, System debug tools (gdb, waveform debuggers), Test plan design and implementation
Preferred skills
Scripting (Python, Perl), UVM and System Verilog, Post-silicon functional validation, Protocol knowledge (PCIe, I2C, Ethernet)
Technologies
Palladium, Veloce, Zebu, C, C++, TCL, System Verilog, UVM, gdb, OpenStack, Docker, Open vSwitch
Responsibilities
Develop innovative emulation environments for multi-terabit system evaluation; Develop emulation infrastructure using C/C++ and TCL; Work closely with design, DV, power, and post-silicon diagnostic teams; Assist with test plan design, implementation, and debugging during the pre-silicon emulation process; Develop tests to generate complex traffic and performance scenarios; Work with leading emulation vendors to solve issues
Seniority
Senior, hands-on IC with technical leadership responsibilities
