ASIC Design Engineer
Core
Design and implement high-performance RTL for next-generation data center silicon subsystems, contributing to architecture and micro-architecture.
Role type
Senior ASIC Design Engineer
Builds
High-performance ASIC subsystems for Cisco core Switching, Routing, and Wireless products
Domain
Data center networking and storage silicon
Deliverable
production ML models | product features
Required skills
Verilog/System Verilog RTL design, timing closure, power optimization, clock gating, ASIC design flows (simulation, synthesis, STA), debug and root-cause analysis
Preferred skills
Data center networking/storage architectures (RDMA, NVMe-over-TCP), ARM-based SoC architectures (AXI, CHI, APB, AHB), high-speed interfaces (PCIe, Ethernet MAC, DDR/LPDDR, DMA), third-party IP integration, engineering scripting (Python, Perl, TCL, shell), emulation/prototyping/formal verification
Technologies
Verilog, System Verilog, Python, Perl, TCL, shell, PCIe, Ethernet MAC, DDR, LPDDR, DMA, AXI, CHI, APB, AHB, RDMA, NVMe-over-TCP
Responsibilities
Contribute to architecture and micro-architecture of high-performance ASIC subsystems; Design and implement high-frequency, high-performance RTL meeting timing, power, and area targets; Develop design and micro-architecture specifications and participate in technical design reviews; Collaborate with verification teams to resolve design issues and drive functional coverage closure; Work with physical design teams to address timing, synthesis, and place-and-route challenges; Debug and root-cause issues across simulation, system integration, and silicon bring-up environments; Contribute to post-silicon validation and lab bring-up to ensure successful silicon delivery
Seniority
Senior, hands-on IC
