FE Engineer
Core
Integrate internal and external IP blocks, designing system bus and control bus logic for connectivity to main SOC infrastructure.
Role type
Senior IC digital design engineer (SoC integration)
Builds
System-on-Chip (SoC) designs with integrated IP blocks
Domain
Semiconductor hardware design
Required skills
System Verilog, Verilog, multi-clock domain design, low power design (clock gating, power gating, DVFS), synthesis tools (Synopsys, Cadence), RTL integration, Design-for-test (scan insertion), CAD tools
Preferred skills
N/A
Technologies
Synopsys, Cadence
Responsibilities
Design system bus and control bus logic for IP connectivity; Integrate and optimize memories and hard macros; Run synthesis, netlist generation, and timing closure; Collaborate with Chip Architecture, Verification, Physical Design, DFT, and Power teams; Develop and maintain design methodology and flows
Seniority
Senior, hands-on IC
