FE RTL Infrastructure - CAD Engineer
Core
Design and maintain infrastructure, version control, and generative AI solutions to support RTL design and verification teams in developing high-performance Apple SoCs.
Role type
Senior IC infrastructure engineer (RTL/CAD)
Builds
Centralized configuration management systems, version control ecosystems, and generative AI tools for engineering productivity
Domain
Semiconductor design / Hardware engineering
Deliverable
infrastructure
Required skills
Python, Perl, Verilog, SystemVerilog, Perforce administration, centralized configuration management, generative AI development
Preferred skills
Front-End EDA tools (Clock Domain Crossing, Reset Domain Crossing, Lint), RTL build/construction flows, large-scale software system development
Technologies
Perforce, Python, Perl, Verilog, SystemVerilog
Responsibilities
Develop and support reliable infrastructure for RTL design and verification; administer Perforce version control; build generative AI solutions to accelerate engineering productivity; maintain centralized configuration management systems; coordinate internal and vendor training materials
Seniority
Senior, hands-on IC
