SoC DRAM Memory Subsystem Validation Engineering Program Manager
Core
Drive memory subsystem readiness, bring-up, validation, and debug for Apple's custom SoCs while helping craft the DRAM industry's mobile roadmap.
Role type
Senior IC Program Manager (SoC DRAM Memory Subsystem)
Builds
High-bandwidth multi-client memory subsystems for Apple SoCs
Domain
Semiconductor / SoC Design / DRAM Technology
Required skills
SoC DRAM Memory Design, Validation, Architecture, Test/Product Engineering, Debugging, Vendor Management, NPI Process Leadership, Cross-functional Team Leadership
Preferred skills
High-performance memory subsystem knowledge, DDR controller/PHY design, High-speed IO interface, DRAM device calibration, High-volume shipping experience, Crisis management, Executive reporting
Technologies
SoC, DRAM, DDR, PHY, DFT, NPI
Responsibilities
Interface and drive memory related silicon issues across multi-functional teams; Drive debug activities in post silicon environments and root-cause problems; Plan and lead adoption of DRAM technologies and custom package development; Work with DRAM Global Supply Management to set priorities; Attend and drive technical sessions with DRAM vendors; Work with silicon material management teams to track distribution; Enable collaboration between DFT, Product/Test/QA, SiVal and Systems teams during NPI; Drive internal program process to guarantee high quality silicon execution.
