SerDes System Validation Engineer
Core
System validation and debug of high-speed SerDes embedded circuits within Apple's SOC/PHY products.
Role type
Senior IC system validation engineer (SerDes/Analog-Mixed Signal)
Builds
High-volume production SoCs with high-speed serial interfaces
Domain
Consumer electronics, high-speed serial communication
Required skills
SerDes system bring-up, mixed-signal verification, DFT definition, robustness analysis, high-speed serial link protocols (PCIe, USB, DP, MPHY), Tx/Rx equalization (CTLE, DFE, de-emphasis), CDR architectures, analog mixed-signal circuit design (Bandgap, LDO, ADC/DAC, Oscillators), scripting and automation
Preferred skills
Analog mixed-signal concepts (mismatch mitigation, linearity, stability), digitally assisted analog design, firmware-assisted mixed signal IP development, AI/ML application for silicon performance
Technologies
PCIe, USB, DP, MPHY, CTLE, DFE, CDR, Python (implied by scripting)
Responsibilities
Own SerDes system bring-up, validation, and debug in system environment; verify operations and analyze robustness/margins; collaborate with design teams to define DFT needs; drive testability features for in-situ validation and debug.
Seniority
Senior, hands-on IC