Formal Verification Engineer
Core
Architecting and leading formal verification efforts for System-on-a-chip (SoC) design blocks and IP, proving design properties, and finding bugs to ensure high-quality functional products.
Role type
Senior IC formal verification architect
Builds
High-quality functional SoC designs and IP blocks (CPU, Cellular, Connectivity, Audio, Image Processing, Neural Networks, Memory/DMA, Security, Interconnects)
Domain
Semiconductor hardware design and verification
Required skills
VLSI and digital logic design, SoC/CPU/GPU/Cellular design, formal property proofs, pipeline architectures, memory/DMA controllers, temporal logic (SVA/PSL), EDA formal tools, scripting languages
Preferred skills
Application processor ISA knowledge, Memory Consistency Models, Cache Coherence protocols, ARM architecture experience
Technologies
SVA, PSL, EDA formal tools
Responsibilities
Develop formal micro-architecture specifications, formalize refinement from architecture to micro-architecture, develop comprehensive formal verification test plans, prove design properties and find bugs, craft novel solutions for complex micro-architectures, develop re-usable formal models and verification code
Seniority
Senior, hands-on IC
