Principal Design Engineer - IP Office
Core
Lead AI SoC design by selecting, integrating, and validating best-in-class IP components (PLL, DTS, HBM4, Ethernet) for AI accelerators.
Role type
Principal Design Engineer (IP Integration & Selection)
Builds
AI System-on-Chip (SoC) components and full SoC integration
Domain
Semiconductor / AI Hardware / SoC Design
Deliverable
production ML models | product features | infrastructure
Required skills
IP selection and qualification, SoC integration, pre/post silicon validation, cross-functional technical leadership, supplier interface management, trade-off analysis
Preferred skills
Experience with 112G/224G Ethernet, PCIe 5/6, HBM3/4, Logic design, Physical design (PD), Design for Test (DFT)
Technologies
112G/224G Ethernet, PCIe 5/6, HBM3/4, PLL, DTS, Droop-Detector, GPIOs
Responsibilities
Identify and select best-in-class IPs for targeted SoC landing zones; Architect robust processes for IP release, update, QA, and integration; Ensure quality of incoming IPs and facilitate smooth integrations with Logic and Physical design teams; Interface with architecture, PD, DFT, and other teams to optimize design tradeoffs; Provide technical leadership through mentorship; Manage interactions with leading IP suppliers.
Seniority
Principal, hands-on IC with strategic supplier management
