Principal Test Engineer
Core
Lead scan (structural) test engineering for semiconductor IC development, covering silicon bring-up, manufacturing readiness, and yield analysis.
Role type
Principal Test Engineer (Scan/Structural Test)
Builds
ATE test programs, scan patterns, and validation flows for logic defects
Domain
Semiconductor / Integrated Circuit Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan architecture, ATPG, fault models, silicon fabrication processes, product qualification, reliability, transistor theory, DFT features (SAF/TDF, JTAG, boundary scan, at-speed testing), scan diagnosis tools, failure analysis, yield improvement, simulation, emulation, pattern verification, mixed-signal IP test interaction, device physics, computer architecture fundamentals, Linux environments, unit and integration testing, test program debugging, optimization, probability, statistics, DOE concepts
Preferred skills
Mixed-signal IP test development, advanced-node designs, high-performance computing, AI, GPUs, telecom
Technologies
Advantest 93K, Linux
Responsibilities
Contribute to silicon bring-up, validation, and manufacturing readiness; Execute defined test plans and methodologies; Identify issues and escalate risks with clear technical data; Collaborate with design, DFT, product, and manufacturing teams; Support scan test content generation, pattern validation, and post-silicon debug; Perform failure analysis using scan diagnosis tools to identify defect locations and support yield improvement; Work with DFT teams on simulation, emulation, and pattern verification
Seniority
Principal, hands-on IC development and strategy
