Senior Silicon Validation Engineer
Core
Lead development of debug tools and infrastructure for validating complex SoCs, including pre-silicon verification, post-silicon validation, and chip bring-up.
Role type
Senior Silicon Validation Engineer
Builds
Debug tools, test firmware, and validation infrastructure for CPUs, GPUs, and vector processors
Domain
Semiconductor hardware validation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
C/C++ development, Python scripting, JTAG tool development, advanced computer architecture knowledge, test planning, failure debugging, high-speed I/O protocols (PCIe, AXI, AHB, I2C, Ethernet), embedded processor debugging, stress scenario creation
Preferred skills
Experience with scan-based methods, FPGA validation, OpenOCD, FTDI interfaces
Technologies
JTAG, OpenOCD, FTDI, C++, Python, PCIe, AXI, AHB, I2C, Ethernet
Responsibilities
Define and deploy methodologies for high-volume test execution, lead silicon power-up using debug tools, develop test firmware for multiple teams, mentor engineers in validation expertise, execute projects with architecture and design teams
Seniority
Senior, hands-on IC
