Quantum Systems Digital Design Engineer II
Core
Design and implement RTL for streaming, low-latency pipelines (readout classifiers, syndrome aggregation, QEC decoder kernels) and high-speed interconnects for quantum systems.
Role type
Senior IC digital design engineer (FPGA/RTL)
Builds
Production FPGA designs for quantum readout and control systems
Domain
Quantum computing hardware / Digital design
Deliverable
production ML models | product features | infrastructure
Required skills
Verilog/SystemVerilog, FPGA synthesis & P&R, high-speed I/O protocols (AXI, JESD204, Aurora, SERDES), clocking & CDC strategies, simulation & constrained-random testing, lab bring-up with RF instruments, CI/CD scripting (Tcl/Python), hardware/software co-design
Preferred skills
UVM, formal verification, HLS (C/C++), RFSoC architectures, graph/union-find/MWPM/LDPC decoder algorithms, signal processing/control concepts
Technologies
Vivado, Vitis, Quartus, Prime, Xilinx/AMD UltraScale+/Versal/RFSoC, Intel platforms, Git, Azure DevOps, VS Code, Python, Tcl
Responsibilities
Design RTL for streaming pipelines and interconnects; develop simulation/testbenches and execute lab bring-up; own synthesis, timing sign-off, and scripted builds; produce design docs and interface specs; participate in system-level design reviews and code reviews.
Seniority
Senior, hands-on IC
