Senior PCIe Bridge Design Verification Engineer
Core
Lead verification of complex Peripheral Component Interconnect Express (PCIe) Bridge IP flows, defining strategies and test plans to drive quality and find bugs.
Role type
Senior IC verification engineer (PCIe IP)
Builds
PCIe Bridge IP and related subsystems
Domain
Hardware verification, PCIe protocol
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, System Verilog, random-stimulus generation, coverage-driven verification, generative AI application, Python scripting, cross-team technical leadership
Preferred skills
Experience with Coherent Hub Interface (CHI) and Advanced eXtensible Interface (AXI) protocols, bottom-up scheduling, full product cycle IP verification
Technologies
UVM, System Verilog, Python
Responsibilities
Develop UVM-based verification environments and run/debug simulations; apply random-stimulus and coverage-based techniques to find bugs; innovate verification methodologies and tools; share expertise through coaching and mentorship; coordinate work across teams to drive verification closure.
Seniority
Senior, hands-on IC with technical leadership
