Senior Test Engineer
Core
Develop and execute scan (structural) test programs for semiconductor ICs, supporting silicon bring-up, validation, and manufacturing readiness across fabrication, test, and packaging phases.
Role type
Senior IC Test Engineer (Scan/Structural Test)
Builds
ATE test programs, scan patterns, and test methodologies for logic defects
Domain
Semiconductor / Integrated Circuit Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan architecture, ATPG, fault models, silicon fabrication processes, product qualification, reliability, transistor theory, DFT features (SAF/TDF, JTAG, boundary scan, at-speed testing), scan diagnosis tools, failure analysis, yield improvement, simulation, emulation, pattern verification, Linux environments, unit and integration testing, probability, statistics, DOE concepts, computer architecture fundamentals
Preferred skills
Mixed-signal IP test development, device physics background, high-performance computing, AI, GPUs, telecom domains
Technologies
Advantest 93K, Linux
Responsibilities
Contribute to silicon bring-up, validation, and manufacturing readiness; Execute defined test plans and methodologies; Identify issues and escalate risks with technical data; Collaborate with design, DFT, product, and manufacturing teams; Support scan test content generation, pattern validation, and post-silicon debug; Perform failure analysis using scan diagnosis tools to support yield improvement
Seniority
Senior, hands-on IC development and test engineering
