Senior Design Verification Engineer
Core
Develop testbenches, write test plans, debug failures, and verify the correctness and functionality of digital designs for semiconductor or systems engineering products.
Role type
Senior Design Verification Engineer (entry-level IC)
Builds
Digital designs and verification methodologies
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features
Required skills
Digital logic design, Computer architecture, Hardware Description Languages (Verilog/VHDL), Verification concepts (simulation, assertions, code coverage), Programming/scripting (Python, C, C++, SystemVerilog), Analytical problem-solving
Preferred skills
Networking protocols (Ethernet, TCP/IP, USB, PCIe), Communication protocols (UART, SPI, I2C, AXI, AMBA), SystemVerilog, UVM, Constrained-random verification, Functional coverage, Assertion-based verification, EDA tools (Synopsys VCS, Cadence Xcelium, Mentor Questa), Scripting automation (Python, Tcl, Perl, Shell), FPGA prototyping, SoC design, Signal processing, Embedded systems, AI/ML applications, Internship experience
Technologies
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Mentor Questa, Python, Tcl, Perl, Shell, Verilog, VHDL, Ethernet, TCP/IP, USB, PCIe, UART, SPI, I2C, AXI, AMBA
Responsibilities
Develop testbenches for digital designs, Write test plans, Debug verification failures, Contribute to improving verification methodologies
Seniority
Senior, entry-level IC
