High-Speed Interface Validation Engineer, Post Silicon Validation
Core
Validating high-speed interconnects (HBM, PCIe, UCIe, SerDes) for AWS ML accelerators to ensure link integrity, performance, and reliability across the product lifecycle.
Role type
Senior IC hardware validation engineer (high-speed interfaces)
Builds
Custom silicon for AWS ML training accelerators
Domain
Semiconductor hardware / High-speed interconnects / AI infrastructure
Deliverable
production ML models
Required skills
High-speed interface validation (HBM, PCIe, UCIe, SerDes), RF measurement equipment operation, signal integrity analysis (eye diagrams, jitter, voltage margin), protocol compliance testing, PVT corner stress testing, silicon debug, equalization tuning
Preferred skills
HBM PHY training sequences, forward error correction (FEC), link reliability metrics (BER, MTBF), PCB/package-level signal integrity, multi-die/chiplet architecture validation, adaptive equalization techniques (CTLE, DFE, FFE)
Technologies
MATLAB, Python, Pearl, oscilloscopes, spectrum analyzers, vector signal generators, network analyzers, power meters
Responsibilities
Validate high-speed interfaces end-to-end from PHY training through sustained traffic; Perform electrical characterization including eye diagrams and jitter analysis; Execute protocol-level compliance and interoperability testing; Stress-test links across PVT corners and aging conditions; Debug link training failures and performance degradation; Collaborate with PHY design teams on equalization optimization
Seniority
Senior, hands-on IC
