DFT Design Engineer, ML Acceleration
Core
Design and optimize hardware for AWS Machine Learning inference and training servers (Inferentia and Trainium) by developing advanced Design for Test (DFT) architectures and ensuring silicon quality.
Role type
Senior IC DFT Design Engineer (ML Acceleration)
Builds
Custom SoCs for Cloud-Scale Machine Learning Acceleration
Domain
Semiconductor / Machine Learning Infrastructure
Deliverable
production ML models | product features
Required skills
DFT architecture design, ATPG, JTAG, MBIST, RTL coding (Verilog/SystemVerilog), gate-level simulation debugging, STA constraint creation, Perl/Python/Tcl scripting, silicon debug
Preferred skills
Masters degree in Electrical/Communications Engineering, experience with advanced technology nodes, experience creating automation scripts
Technologies
AWS Cloud, Perl, Python, SystemVerilog, Verilog
Responsibilities
Define and develop advanced DFT architectures for leading-edge technology nodes, Write RTL code and perform verification, Generate high-coverage test patterns, Contribute to silicon debug efforts, Collaborate with block and physical design teams
Seniority
Senior, hands-on IC
