Staff ASIC Modeling Software Engineer
Core
Design and implement high-fidelity C++ software components to simulate ASIC behavior, including forwarding engines, schedulers, and memory subsystems, enabling software development and verification before silicon availability.
Role type
Staff ASIC Modeling Software Engineer
Builds
Simulation platform for next-generation AI networking ASICs
Domain
Semiconductor / AI Networking
Deliverable
production ML models
Required skills
C/C++ architecture model development, cycle-aware simulation, ASIC verification, modern C++ programming, network switch/router architecture, packet-processing pipelines, dataplane simulation, gRPC, Protocol Buffers, C++ unit-testing frameworks, Python for test automation, debugging across software/hardware domains
Preferred skills
AI/ML networking, ns-3, HTSim, SAI, SONiC, FPGA prototyping, memory subsystem modeling, configuration-driven simulation frameworks
Technologies
C++, Python, SystemVerilog, Verilog, gRPC, JSON, YAML, Protocol Buffers, RDMA, FPGA
Responsibilities
Design and implement software components that simulate ASIC behavior, Convert architectural specifications into high-fidelity C++ models, Develop and maintain register models and memory maps, Optimize model performance for large-scale simulations, Collaborate with RTL engineers to ensure correlation between model and silicon, Partner with SDK and platform software teams to support validation
Seniority
Staff, hands-on IC
