Senior FPGA / RTL Design Engineer - Signal Processing
Core
Senior FPGA/RTL Design Engineer implementing novel signal processing algorithms for MIMO wireless networking products.
Role type
Senior IC FPGA/RTL Design Engineer (Signal Processing)
Builds
FPGA-based designs for advanced wireless systems R&D and MANET radios
Domain
Defense, law enforcement, public safety; Wireless communications (MANET, MIMO)
Deliverable
production ML models
Required skills
FPGA design, RTL coding, simulation, test bench development, FPGA synthesis, timing closure, hardware verification, fixed-point arithmetic, digital signal processing, multi-clock-domain design, Xilinx FPGAs, Vivado IDE
Preferred skills
MATLAB, communication systems on FPGA or ASIC
Technologies
Xilinx, Vivado, FPGA, RTL, MATLAB
Responsibilities
Digital design architecting for wireless communication projects, Fixed point design of signal processing blocks, RTL coding, simulation, and test bench development, FPGA synthesis and timing closure, Hardware verification and troubleshooting, Provide support to RF and Software Engineering teams
Seniority
Senior, hands-on IC
