Principal FPGA / RTL Design Engineer - Signal Processing
Core
Architecting digital designs and implementing signal processing algorithms for MIMO wireless networking products.
Role type
Principal FPGA / RTL Design Engineer
Builds
MIMO wireless networking radios and advanced wireless systems
Domain
Defense, law enforcement, public safety communications
Deliverable
production ML models
Required skills
RTL design, FPGA implementation, fixed-point arithmetic, digital signal processing, multi-clock-domain design, Xilinx Vivado
Preferred skills
MATLAB, Python/Perl scripting, wireless communication systems on FPGA/ASIC
Technologies
Xilinx FPGAs, SoCs, Vivado IDE, logic analyzers
Responsibilities
Digital design architecting for wireless communication projects, Fixed point design of signal processing blocks, RTL coding, simulation, and test bench development, FPGA synthesis and timing closure, Hardware verification and troubleshooting, Provide support to RF and Software Engineering teams
Seniority
Principal, hands-on IC
