Principal PLL IC Design Engineer - TeraWave
Core
Lead the design, development, and integration of high-performance integrated Phase-Locked Loops (PLLs) and clocking systems for advanced space communication satellites.
Role type
Principal IC Design Engineer (Analog/RF mmWave)
Builds
Integrated PLLs and clock distribution circuits for optically interconnected LEO/MEO satellite constellations
Domain
Aerospace / Satellite Communications / mmWave RF
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
High-speed PLL design (>20GHz), mmWave frequency expertise, loop design for phase noise/jitter/spur optimization, CMOS FinFET and SiGe process knowledge, clock domain synchronization, mixed-mode and RF modeling, silicon characterization and debugging, analog/RF building block design (amplifiers, mixers, filters)
Preferred skills
Fractional-N PLL design, All-Digital PLL (ADPLL) design, sub-sampling PLL design, LDO and bias generator design, operational amplifier design, digital verification and SystemVerilog modeling
Technologies
Spectre, AMS flows, MATLAB, SystemVerilog, CMOS FinFET, SiGe
Responsibilities
Lead design and integration of PLLs in advanced CMOS/SiGe technologies; Utilize Spectre and AMS flows for high-performance circuit development; Collaborate with RF and SOC system architects to define requirements; Oversee layout, floorplanning, and verification for tape-out; Develop test plans and facilitate bring-up with validation engineers; Investigate and implement fundamental analog building blocks; Mentor junior engineers in analog design practices
Seniority
Principal, hands-on IC with mentorship
