Product Engineering Architect – High-Speed IP PHY
Core
Primary technical team leader and product owner driving product engineering activities for high-performance interface IP (UCIe, PCIe, USB, DPHY, Ethernet, DDR, LPDDR, GDDR, HBM) from pre-sales to post-silicon deployment.
Role type
Senior IC Product Engineering Architect (High-Speed IP PHY)
Builds
High-performance digital and mixed-signal IP solutions for SoC integration
Domain
Semiconductor / High-Speed Interface IP
Required skills
High-speed interface IP expertise, RTL design, gate-level verification, simulation methodologies, synthesis, STA, timing closure, DFT methodologies, system validation, cross-functional leadership, complex problem solving, customer-facing technical leadership
Preferred skills
Memory and high-speed communication interfaces (DDR, LPDDR, PCIe, Ethernet, UCIe, USB), analog/mixed-signal design practices, silicon debug and bring-up environments, AI-assisted workflows
Technologies
UCIe, PCIe, USB, DPHY, Ethernet, DDR, LPDDR, GDDR, HBM, RTL, Gate-level simulation, Synthesis, STA, DFT
Responsibilities
Lead customer engagements and technical discussions for high-speed interface IPs, Own resolution of complex subsystem integration and implementation issues, Lead SoC integration reviews covering PHY and controller subsystems, Provide technical leadership for RTL, gate-level simulations, and timing closure strategies, Lead post-silicon bring-up and debug activities, Mentor and lead team members and provide technical guidance
Seniority
Senior, hands-on IC with team leadership